The present invention relates to a cyclic noise reducing apparatus for reducing noise in a video signal using the field correlation of the video signal.
A video tape recorder of the prior art is designed to record a chrominance signal in a low frequency range and to frequency multiplex this signal on a frequency modulated luminance signal. However, when a luminance signal including noise is demodulated during recording or playback, a triangular noise characteristic of the frequency modulation/demodulation system increases as the frequency increases. Accordingly, before the luminance signal is modulated, high frequency portions of the luminance signal are generally emphasized using a pre-emphasis circuit, and a de-emphasis circuit is used to restore the pre-emphasized signal to its original form for signal playback. However, because the de-emphasized luminance signal still includes noise, a cyclic noise reducing apparatus such as that shown in FIG. 1 may need to be connected to the de-emphasis circuit to eliminate this noise.
The cyclic noise reducing apparatus shown in FIG. 1 suppresses the noise component using the difference between the noise with a high field correlation and a video signal which is almost free from field correlation. The noise component is suppressed by cyclically adding the output video signal to an attenuated input video signal. The input video signal is first supplied to an adder 3 through an attenuator circuit 2 with a gain of 1-K, where 0&lt;K&lt;1. The adder 3 receives as one input the output video signal via a positive feedback circuit including a field memory circuit 4, a line memory circuit 5, and an attenuator circuit 6. The input video signal is also received by the adder as a second input. The positive feedback circuit is arranged so that the line memory circuit 5 for storing and delaying video signals corresponding to one line is connected in series to the field memory circuit 4 which stores and delays video signals corresponding to a field (262 lines for NTSC) and so that a gain of K is applied to the delayed signal by attenuator circuit 6. As a result, an output video signal corresponding to an input signal delayed by an extra line (263 lines for NTSC) is also attenuated and positively fed back. In this case, the closer the gain K of attenuator 6 is to 1, the higher the degree of signal to noise (SN) improvement obtained by the cyclic noise reducing apparatus of FIG. 1.
The conventional cyclic noise reducing apparatus of FIG. 1 utilizing the field correlation is advantageous in that the storage capacity required is only half that of a frame memory circuit, and even when displaying animated cartoons which are normally fast in motion, a ghost image is less noticeable than when frame correlation is used. On the other hand, the image signal circulating through the series circuit consisting of the field memory circuit 4 and the line memory circuit 5 is delayed by approximately 1/2 line relative to the inputted line each time it is fed back. In this case, the quantity thus added by positive feedback is multiplied by a gain K raised to the nth power, where n is the number of cycles, and the greater the number of cycle repetitions n made by a signal becomes, the less the influence upon the output exhibited by the fed back signal when it is added. However, because the signals gradually lose correlation each time they are fed back and added together, the response of the output video signal to an input video signal rising in step forms, as shown in FIG. 2A, is represented by a step waveform at a line pitch during its rising time, thereby exhibiting a curved change similar to the step response of a general low-pass filter circuit as shown in FIG. 2B. In FIGS. 2A and 2B, this phenomenon is represented by continuous and dotted lines which designate signals of even and odd number fields, respectively. This shortcoming is inherent in the cyclic noise reducing apparatus of FIG. 1 and causes deterioration in vertical resolution.
As a further example, in the cyclic noise reducing apparatus shown in FIG. 3, a line memory circuit 5 connected to a field memory circuit 4 and a signal line 8 bypassing the line memory circuit 5 are connected to an adder 9 in parallel, and an attenuator circuit 10 for attenuating the sum signal level by 1/2 is connected between the adder 9 and attenuator circuit 6. The arrangement of FIG. 3 was proposed to reduce noise by causing the mean value of a first video signal delayed by the field memory circuit 4 to be delayed by a field (262 lines) and a second video signal delayed by the line memory circuit 5 to be delayed by one additional line (263 lines).
The vertical resolution in the FIG. 3 cyclic noise reducing apparatus would appear to experience less deterioration than the apparatus of FIG. 1. However, as is obvious from the step response output shown in FIG. 4B, responsive to the step response input shown in FIG. 4A, the signal delayed by 262 lines and the signal delayed by 263 lines form step waveforms at a line pitch in front or behind the rising of the step input. As in the FIG. 1 apparatus, the vertical resolution is deteriorated by the FIG. 3 apparatus in the manner shown.